Following the previous article describing the concept of power-saving solenoid driver, in this article we want to further develop this topic and present an implementation project using SLG47105.

The complete internal SLG47105 design is shown in Figure 1. The following sub-sections will explain each part of this design. This design was created in the Go Configure Software Hub’s GreenPAK Designer project (the design file is available here).

click for full size image Figure 1. Overview of the complete SLG47105 internal design

Figure 2 shows the OSC1 block and its internal configuration. The OSC1 block is the oscillator that supplies a clock signal for the PWM Controller blocks. The clock frequency is 6.25 Mhz. This block is always turned on.

click for full size image Figure 2. OSC1 block signals and internal configuration

Figure 3 shows the OSC0 block and its internal configuration. OSC0 supplies a clock for the start-up delay block and the low-frequency square wave generator.

click for full size image Figure 3. OSC0 block and its internal configuration

Figure 4 shows all the blocks used for the start-up time delay functionality. The main block in this functionality is the CNT0/DLY0/FSMO component. Its configuration is shown in Figure 4. The CNT0 will delay for almost 2 milliseconds the inverted POR signal, raising a positive edge in the READY signal connection after this initial time. This initial start-up time is required to guarantee that all internal and external components (power supply and capacitors) are ready to properly drive the power outputs and regulate the solenoid current.

click for full size image Figure 4. Start-up time delay block. The CNT0/DLY0/FSM0 configuration is shown on the left side

Figure 5 shows the HVOUT CTRL0 connections and their internal configuration. HVOUT CTRL0 is the block that controls the SLG47105 internal power transistors.

click for full size image Figure 5. HV OUT CTRL0 block connections and configuration

This block controls the power transistors connected to the S1 solenoid. At power-up the block is deactivated. It is activated by the inverted POR signal connected in Sleep0 and Sleep1 inputs. The output of Pin 8 is always set to activate the push-pull low side by the same inverted POR signal connected in the input IN1. However, the output transistors are only active when the READY signal connected to the OE1 input is at a high level. The push-pull output of Pin 7 is entirely controlled by the PWM Controller block (its operation will be explained below).

Furthermore, the HVOUT CTRL 0 block supplies the FAULT_A signal to indicate when a fault condition occurs in this power output.

The HVOUT CTRL 1 block is configured in the same way as the HVOUT CTRL 0 block. Its connections behave similarly and have similar purposes. The HVOUT CTRL 1 block is connected to the S2 solenoid through Pins 9 and 10. This block is connected to the PWM Controller 2 block and it supplies the FAULT_B signal for any fault in its operation.

PWM Controller and Current Regulation

Figure 6 shows the PWM Controller 1 block inside a yellow box. This block is formed by four components: PWM0, PWM Chopper 0, CNT1/DLY1, and LUT (Look-Up Table) 2-L1 configured as an AND gate. These four components adjust the PWM output for solenoid S1 accordingly to the signal supplied by the current comparator CCMP0.

click for full size image Figure 6. PWM Controller 1 block is inside the yellow box

On the left side of Figure 6 is the internal configuration of the PWM0 block. The PWM0 block generates a complementary PWM with dead-band time. The two complementary PWM signals are used in the 2-L1 AND port to enable/disable the HV GPO0 output. HV GPO0 is disabled before it turns on the high-side transistor as a protective measure. The OUT+ output of the PWM0 block is connected to the PWM Chopper 0 to be chopped by the current comparator CCMP0 signal. PWM Chopper 0 has its blanking input connected to CNT1/DLY1. The CNT1/DLY1 will generate a short pulse of 200 nanoseconds to the blanking time input, allowing a minimum PWM on time. The output of PWM Chopper 0 is connected to the IN0 input of the HV OUT CTRL0 block, controlling the push-pull output of HV GPO0. As seen in Figure 6, the PWM0 block supplies a dynamic reference for the current comparator CCMP0. PWM0 is configured to use the Register File Data to set up the maximum PWM and the reference voltage for the current comparator. There are only two values in use, the first one for the peak current, byte 8, and the second one for the hold current, byte 9. The change of configuration will happen when a positive edge raises in the PWM0 input Duty Cycle CLK.

The components connected to the input of the PWM0 block are shown in Figure 7. The components are an AND gate connected to the PWR DOWN input of PWM0 and CNT3/DLY3 connected to the Duty Cycle CLK input of PWM0. The AND gate operates as an enabler for the S1 On/Off pin signal. The signal from this pin can turn on the PWM0 block just after the start-up delay time when the READY signal is at a high level.

click for full size image Figure 7. Input connections for the PWM0 component

The output of the AND port turns on the PWM0 block and is delayed by 50 milliseconds in the IPEAK TIME delay component. The delay of this block controls how long the PWM will regulate the solenoid current at its peak value. After this time, a positive edge is generated for the Duty Cycle CLK input of PWM0, and the reference register byte is increased, changing the PWM value and the reference voltage for the current comparator CCMP0. When SOL1_CMD is at a high level the PWM0 output is turned on and when SOL1_CMD is at a low level the PWM0 output is immediately turned off.

The current comparator CCMP0 is used to regulate the solenoid current, and the configuration of this component is shown in Figure 8. The current comparator internally amplifies the voltage in Pin 5 by 8 (see IN+ gain in Figure 8).

click for full size image Figure 8. CCMP0 configuration and connection to PWM Chopper 0

This multiplier factor must be considered when setting the reference voltages for comparison. The component is turned on with the inverted POR signal and it is always on after POR. The IN- input of CCMP0 is connected to the PWM0 CCMP0 VREF output. This output will supply the voltage references of bytes 8 and 9 of the Register File Data. The Register File Data is shown in Figure 9.

Figure 9. Register Data File configuration

The structure of PWM Controller 2 is like the structure of PWM Controller 1. The register bytes used for current regulation are bytes 0 and 1. The components of PWM Controller 2 are shown in Figure 10. It is important to note that the solenoid current settings are different in PWM Controller 1 and PWM Controller 2. The current regulation is independent, as are the PWM values.

click for full size image Figure 10. PWM Controller 2 structure and connections

Solenoid Status Indication and Fault Signal

Figure 11 shows the components used for solenoid status indication and fault output signal. The Pipe Delay component is used to generate the 1Hz square wave signal. Its configuration is shown on the left side of Figure 11. This component divides the OSC0 output clock to generate this square wave signal. The signals FAULT_A and FAULT_B are the fault signals for the respective solenoids S1 and S2. These signals are registered to avoid glitches in the output pins. The respective pins are configured as open drain outputs. The output pins connected to the solenoid status indicators are configured as push-pull outputs.

click for full size image Figure 11. Solenoid status indication and fault output signal

The I2C is kept active in the design, allowing users to set PWM values through an external device. There are no internal signals connected to the I2C block, just the respective external pins connected to it.

Figure 12 shows a picture of the verification prototype built to test this design. The prototype was assembled on a breadboard using the SLG47105 DIP Board.

click for full size image Figure 12. Verification prototype

The prototype testing procedure consists of pressing the respective solenoid pushbutton and then verifying the following:

Plunger movement and position: The solenoid plunger must be pulled-in when it is activated by the driver. The driver must hold the plunger in the pulled-in position while it is active. The driver must release the plunger from its pulled-in position and return it to the de-energized position when the driver is deactivated.

LED indicators: When the solenoid is deactivated its green LED indicator must be off. When it is activated its green LED indicator must be on. When the respective solenoid output has a fault condition (short circuit) the solenoid green indicator must blink at a frequency of 1Hz. The fault red LED indicator must be on when there is a fault condition and off otherwise.

Current measurement: the maximum peak and hold currents must be measured and should comply with the designed values.

To measure the current through the solenoids we added a small resistor of 0.1Ω (0.1 percent) in series with each solenoid.

The voltage through this resistor is measured using two channels of an oscilloscope. The oscilloscope used is the Hantek 6022BE. The current in Ampères will be:

Figure 13 shows the measured current when activating the solenoid S1. The figure shows the initial peak current through the solenoid and, after 50.7 milliseconds, the current reduction to the hold value.

click for full size image Figure 13. Solenoid S1 current measurement. The current is shown through the math channel M, which is equal to (CH1 – CH2)

Figure 14 shows a close view of the peak current and the measurement of its value. The measured peak current value is 113mV, corresponding to 1.13A.

click for full size image Figure 14. Solenoid S1 close view of peak current measurement. The cursor is positioned over the math channel M, where M = (CH1 – CH2)

Figure 15 shows a close view of the hold current measurement. The measured maximum hold current is 25.5mV, equivalent to 255mA.

click for full size image Figure 15. Solenoid S1 close view of hold current measurement. The cursor is positioned over the math channel M, where M = (CH1 – CH2)

Figure 16 shows the PWM generated in Pin 7 (HV_GPO0) during the activation of solenoid S1 (peak current setting). Figure 16 reveals the reduction of the PWM duty cycle over time.

click for full size image Figure 16. Solenoid S1 peak current PWM applied

Figure 17 shows the PWM applied in the solenoid S1 when it is in hold current regulation. The cursor in the figure shows the high-side transistor on time.

click for full size image Figure 17. Solenoid S1 PWM generated in hold current regulation

Figure 18 shows the voltage at the sense resistor used by SLG47105 to measure the solenoid current in hold current regulation.

click for full size image Figure 18. Solenoid S1 voltage in sense resistor with driving solenoid in hold current regulation

Figure 19 shows the PWM applied to the solenoid S1 when it is short-circuited (a fault condition).

click for full size image Figure 19. Solenoid S1 driver PWM when the output is short-circuited

Figure 20 shows the measured current when activating the solenoid S2. The figure shows the initial peak current through the solenoid and, after nearly 50 milliseconds, the current reduction to the hold value. Before the current regulation switch from peak to hold value, there is a visible fall in the measured current. The reason for this valley is the back electromagnetic force (EMF) generated by the moving core of the solenoid (the plunger). When the plunger starts to move, its movement in the magnetic field of the solenoid induces a current in the coil winding against the current that is pulling the core into the solenoid. This effect ends when the plunger arrives at its limit point and stops moving.

click for full size image Figure 20. Solenoid S2 overview of the current measurement. The current is shown through the math channel M, which is equal to (CH1 – CH2)

Figure 21 shows a close view of the peak current and the measurement of its value. The measured peak current is 66.5mV, meaning a peak current value of 665mA.

click for full size image Figure 21. Solenoid S2 close view of peak current measurement. The current is shown through the math channel M, which is equal to (CH1 – CH2)

Figure 22 and Figure 23 show a close view of the hold current and the measurement of its value. Figure 22 shows the cursor value in Channel1 and Figure 23 shows the cursor value in Channel 2. The cursor reading in Channel 1 is 55.4mV and in Channel 2 is 38.7mV. The difference between them is equal to 16.7mV, meaning a current of 167mA in the solenoid.

click for full size image Figure 22. Solenoid S2 close view of hold current. The cursor is positioned at the peak of channel 1

click for full size image Figure 23. Solenoid S2 close view of hold current. The cursor is positioned at the peak of channel 2

Figure 24 shows the PWM applied in the solenoid S2 when it is in hold current regulation.

click for full size image Figure 24. Solenoid S2 view of applied PWM in hold current regulation

Figure 25 shows the voltage at the sense resistor used by SLG47105 to measure the solenoid current in hold current regulation.

click for full size image Figure 25. Solenoid S2 voltage in sense resistor with driving solenoid in hold current regulation

Table 1 shows a comparison between the calculated and measured peak and hold currents of each solenoid.

Table 1. Comparison of measured and calculated currents. All current values are in mA.

Table 2 shows a comparison between the calculated and measured (considering the measured current and nominal resistance) power of each solenoid.

Table 2. Comparison of measured and calculated power dissipations. All power values are in mW

Table 3 shows the calculated and measured power savings achieved with the power saving solenoid driver. The nominal power consumption is considered for this calculation.

Table 3. Comparison of calculated and measured power saving

This article showed the implementation of a dual power-saving solenoid driver. It was shown that the driver can achieve huge power savings for the two solenoids, depending on the ratio of hold current to peak current. The higher the ratio, the higher the power saving. However, it is important to say that the ratio depends on the application. Reducing the hold current will reduce the force to maintain the plunger pulled in the solenoid.

It is important to discuss the results shown in the comparison of the calculated and measured currents (see Table 1 again). The hold current had a significant error, higher than 10 percent, for both solenoids. From the analysis of the absolute and percentual current errors it is possible to say that there are side effects of gain and offset errors. As shown in Table 1, the absolute error increases with the current setpoint, which is a signal of gain error. This gain error can be associated with limitations in the sense resistor accuracy. However, the increase in the percentual error when the current is reduced to the hold value indicates an offset error. This means an almost constant error, and that will be more relevant for lower values. It seems that the offset error is more relevant than the gain error. Unfortunately, is not possible to identify the source of this error. Some of the hypotheses are an error in the SLG47105 current comparator or an error in the current measurement made with the oscilloscope.

Note: All images and tables are courtesy of Renesas Electronics Corp.

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